The present invention relates to a multistage amplifier circuit constituted by cascade-connecting at least two field effect transistors (FETs), and more particurlarly to a simplified feedback type amplifier circuit which can improve frequency characteristics in a low frequency range.
Initially, a two-stage amplifier circuit as an example of a conventional multistage amplifier circuit constituted with at least two FETs cascade-connected to each other will be described with reference to FIG. 1. This amplifier circuit comprises a first-stage FET 1, the next (second)-stage FET 2 cascade-connected to the FET 1, and an interstage capacitor 3 connected between a drain D.sub.1 of the FET 1 and a gate G.sub.2 of the FET 2. Both drains D.sub.1 and D.sub.2 of the FETs 1 and 2 are connected commonly to a drain bias power supply terminal 6 through load impedances 4 and 5, respectively. Further, sources Shd 1 and S.sub.2 are grounded and gates G.sub. and G.sub.2 are connected to a gate bias terminal 9 through gate bias power feed impedances 7 and 8, respectively. To provide a flat gain over a wide frequency band, a first amplifier stage comprised of the FET 1 is provided between the drain D.sub.1 and the gate G.sub.1 with a series circuit comprising first-stage feedback network 10 and a capacitor 11 for blocking a dc component of a feedback signal (which will be called a dc block capacitor 11 hereinafter). Likewise, the second amplifier stage comprised of the FET 2 is provided between the drain D.sub.2 and the gate G.sub.2 with a series circuit comprising a second stage feedback network 12 and a capacitor 13 for blocking a dc component of a feedback signal (which will be called a dc block capacitor 13 hereinafter). The amplifier circuit further comprises an input terminal 14 which is connected to the gate G.sub.1 of the FET 1, and an output terminal 15 which is connected to the drain D.sub.2 of the FET 2.
In the amplifier circuit thus configured, when an input signal is supplied to the gate G.sub.1 through the input terminal 14, the input signal is amplified by the FET 1. The amplified output from the drain D.sub.1 of the FET 1 is inputted to the gate G.sub.2 through the interstage capacitor 3 and then is amplified by the FET 2, thus producing an output signal on the output terminal 15 connected to the drain D.sub.2 of the FET 2. In this amplifier circuit, negative feedbacks are implemented to both the FETs 1 and 2 through the first-stage feedback network 10 and the dc block capacitor 11 and through the second-stage feedback network 12 and the dc block capacitor 13, respectively.
However, since the conventional multistage amplifier circuit configured as shown in FIG. 1 is provided with a feedback circuit per each amplifier stage, it requires dc block capacitors 11 and 13 in the respective feedback loops in addition to the interstage dc block capacitor 3.
For this reason, in general, when n stages of amplifiers are configured with such a conventional amplifier circuit, (2n-1) capacitors are required, leading to the drawbacks that circuit configuration becomes complicated and this conventional system is not economical. In addition, it has the drawback in characteristics that frequency characteristics of the amplifier in a low frequency range is limited by the capacitance, except for the interstage capacitor, existing in each feedback loop.
Further, when the above-mentioned amplifier circuit is configured as an integrated circuit (IC), the total capacitance value of capacitors has a great influence on the IC size to such a degree that it determines the IC size. For this reason, it is strongly required that the capacitance value of capacitors in the IC is as small as possible. To satisfy this requirement, first is to take the measure for reducing the number of capacitors used and second is to take the measure for configuring the IC at a minimum capacitance value required.